This invention relates to dynamic signal generation circuits used for MOS integrated circuits and the like for generating a delayed clock signal by raising the voltage of an input clock signal through a capacitor-coupled bootstrap circuit.
The N-channel MOS (Metal Oxide Semiconductor) integrated circuit generally makes effective use of a dynamic signal generation circuit, which includes a load transistor and a drive transistor both being of the enhancement type, in order to reduce power consumption. In such a dynamic signal generation circuit, a capacitor-coupled circuit (or bootstrap circuit) for raising the input signal voltage is connected to a necessary node (circuit junction) for making up the signal amplitude attenuation that naturally results from the use of the enhancement type load transistor and corresponds in amount to the threshold voltage component.
A typical dynamic signal generation circuit of this sort which is extensively used for such integrated circuits is a MOS RAM (Random Access Memory) has a construction as shown in FIG. 1. Reference numeral 12 designates a semiconductor circuit, which receives input clock signals .phi. and .phi. (FIGS. 2A and 2B) and provides output signals .phi.1 and .phi.2, which will be described later, from its first and second output terminals 14 and 16 respectively. This semiconductor circuit includes a plurality of N-channel enhancement transistors. The dynamic signal generation circuit also comprises N-channel enhancement transistors T11, T12, T13 and T14, a power supply terminal 18 which is connected to a first power supply source at a potential V.sub.DD, and another power supply terminal 20 connected to a second power source at a potential V.sub.SS. The first output terminal 14 of the semiconductor circuit 12 is connected to the gate of the transistors T11 and T13 and also connected to one end of a capacitor C (this junction being hereinafter referred to as node N1). The transistors T11 and T13 have their drain connected to the V.sub.DD power supply terminal 18. The transistor T11 has its source connected to the other end of the capacitor and also to the drain of the transistor T12 (this junction being hereinafter referred to as node N3).
The second output terminal 16 is connected to the gate of the transistor T13 (this junction being hereinafter referred to as node N2), and is also connected to the gate of the transistor T14. The transistors T12 and T14 have their sources connected to the V.sub.SS power source terminal 20. The transistor T14 has its drain connected to the source of the transistor T13 (this junction being hereinafter referred to as node N4). An output signal .phi.d is provided from this node N4. Enclosed within a dashed rectangle is a bootstrap circuit 22.
The output signal .phi.1 of the semiconductor circuit 12, as shown in FIG. 2C, rises to the potential V.sub.DD in synchronism to the rising of the input clock signal .phi. shown in FIG. 2A (or in synchronism to the falling of the input clock signal .phi. as shown in FIG. 2B). After the lapse of a delay time in the operation of the semiconductor circuit 12, the output signal assumes a floating state having a high potential level V.sub.P (which is equal to V.sub.DD +V.sub.TE, V.sub.TE being the threshold value of each transistor), and it falls to a low potential level V.sub.SS in synchronism to the falling of the input clock signal .phi. or in synchronism to the rising of the input clock signal .phi.. The output signal .phi.2 (FIG. 2D), on the other hand, falls to the potential level V.sub.SS in synchronism to the rising of the output signal .phi.1 to the potential level V.sub.P =(V.sub.DD +V.sub.TE) and rises to the potential level V.sub.DD in synchronism to the falling of the input clock signal .phi. or rising of the input clock signal .phi..
The dynamic signal generation circuit of FIG. 1 described above operates as follows.
In the stand-by state, i.e., at an instant t.sub.s, the node N1 is at the low potential, the node N2 is at the high potential, and the nodes N3 and N4 are at the low potential. With the rising of the input clock signal .phi.1, the node N1 commences to be charged. At this time, the node N2 remains at the high potential V.sub.DD. When the charging mentioned above has proceeded to a certain extent or is completed, the input clock signal .phi.2 falls to discharge the node N2. Assuming for the sake of simplicity that the threshold voltages of the individual transistors T11 to T14 are all equal (and lower than V.sub.TE, with 0&lt;V.sub.TE &lt;V.sub.DD), the transistors T11 to T14 are all "on" from the instant when the potential on the node N1 being charged exceeds V.sub.TE till the instant when the potential on the node N2 being discharged becomes lower than V.sub.TE. During this period, feedthrough current flows from the V.sub.DD power supply terminal 18 through the transistors T11 and T12 to the V.sub.SS power supply terminal 20, and also flows from the V.sub.DD power supply terminal through the transistors T13 and T14 to the V.sub.SS power supply terminal 20. Also, during this time, the node N3 is held at a low potential (referred to as potential V.sub.L) which is determined by the conductance ratio between the transistors T11 and T12.
The discharge of the node N2 is caused when a certain voltage difference is developed between the nodes N1 and N2, i.e., across the capacitor C. With the discharging of the node N2, the transistors T12 and T14 are turned off to cause charging of the node N3 from the potential V.sub.L to the high potential. As a result, the output terminal 14 of the semiconductor circuit 12, from which the output signal .phi.1 is provided, assumes a high impedance state, that is, the node N1 assumes a floating state. The potential on the node N1 is thus raised from the potential V.sub.DD to the high potential V.sub.P due to the capacitance coupling of the nodes N1 and N3 by the intermediate capacitor C. The potential V.sub.P is desirably higher than V.sub.DD +V.sub.TE. If this condition is satisfied, the node N4 is also charged up to the potential V.sub.DD. Consequently, the output signal .phi.d, shown in FIG. 2E, which is delayed behind the input clock signal .phi. to the semiconductor circuit 12, is obtained from the node N4. The falling of the input clock signal .phi. causes the node N1 to return to the low potential and the node N2 to the high potential. As a result, both the nodes N3 and N4 are discharged to recover the initial state.
In the dynamic generation circuit of the prior art as described above, however, the feedthrough current from the instant when the node N1 begins to be charged till the instant when the node N2 begins to be discharged is high and not ignorable from the standpoint of power consumption and source voltage fluctuations. Particularly, the feedthrough current through the transistors T13 and T14, which must have high conductance for charging and discharging the node N4 which is connected to a high capacitance load is higher than the feedthrough current through the transistors T11 and T12 and presents problems in regard of power consumption and influence on source voltage fluctuations.
Therefore, the feedthrough current, and hence the effects on source voltage fluctuations, is desirably reduced.